1. Field of the Invention
The present invention relates to a semiconductor memory device, and, in particular, to a semiconductor memory device including a circuit for analyzing defects in word-lines.
2. Description of the Related Art
Generally, a semiconductor memory device includes a memory cell array in which memory cells are arranged at intersections of word-lines and bit-lines. Data is written in or read out from a given memory cell within the memory cell array, when the word-line and the bit-line connected to the memory cell in question are selected by a row decoder and a column decoder.
The selection of word-lines is performed by the row decoder for decoding row address signals. The row decoder includes a plurality of word-line drive circuits for setting the potential of a selected word-line to a predetermined value, in addition to a plurality of decoding circuits for decoding row address signals.
Recently, there has been considerable demand for a large-capacity, high-speed semiconductor memory device, and to meet such demand, each memory cell of the memory device has been miniaturized. In addition, minimum design size for a transistor has been reduced. Since the area of each memory cell is a most important factor in determining the area of a chip, the pattern of memory cells has been designed in accordance with minimum design size.
Since the arrangement of word-lines is determined by the arrangement of the memory cells, the pitch of the word-lines becomes narrower as the pattern area of each memory cell is reduced. The decoding circuits and drive circuits need to be arranged on the chip at a pitch corresponding to the arrangement of memory cells, due to the fact that each word-line requires one decoding circuit and one word-line drive circuit. Since most of the area of a chip is taken up by the memory cells and by the decoding and drive circuits, therefore these circuits are normally formed in accordance with minimum design size.
However, when a circuit is designed on this basis, defects are likely to occur in the elements thereof, even when a mask-alignment is slightly displaced during the manufacturing process. Such defects may lead to malfunctions. In particular, since the decoding circuits and the word-line drive circuits include a great number of elements, compared to other peripheral circuits, there is a great possibility that defects may occur in these two circuits.
For example, when a short circuit, a leakage, or an imperfect contact occurs between a gate and a substrate in a transistor constituting a decoding circuit or a word-line drive circuit, the potential of the word-line may be fixed to "L" level. Normally, this potential is set at "H" level in the selected state, and at "L" level in the non-selected state. Memory cells connected to a defective word-line will always be kept in the nonselected state, preventing normal memory access.
In some cases, the logic levels "H" and "L" may be reversed owing to defects in elements of the decoding circuits and the drive circuits, and may result in a word-line, which should correctly be set in the nonselected state, being erroneously set in the selected "H" state. In such a case, memory cells connected to the defective word-line as well as those connected to the normal word-line may be selected, preventing normal data access.
As stated above, in a highly integrated semiconductor memory device, a word-line which should correctly be in the selected state may be set at the potential of the non-selected state, while a word-line which should correctly be in the non-selected state may be set at the potential of the selected state. Consequently, the greater the capacity and integration density of the memory device, the greater the possibility of such malfunctions occurring.
Defective word lines in an initial produce development stage are more likely to be defective because of immature manufacturing techniques. In order to find defective elements, it is necessary to measure levels at nodes within the decoding circuit and the word-line drive circuit by use of an electron beam tester, or to write a special data pattern in the memory device. However, such a defect-finding process is time consuming and inefficient, and inevitably results in a memory device of high manufacturing cost.